1. Field of the Invention
The present invention relates to optical interfaces and, more particularly, to a method and apparatus for aligning multiple SERDES outputs of an FPGA.
2. Description of the Related Art
Data communication networks may include various computers, servers, nodes, routers, switches, bridges, hubs, proxies, and other network devices coupled to and configured to pass data to one another. These devices will be referred to herein as “network elements.” Data is communicated through the data communication network by passing protocol data units, such as Internet Protocol packets, Ethernet Frames, data cells, segments, or other logical associations of bits/bytes of data, between the network elements by utilizing one or more communication links between the network elements. A particular protocol data unit may be handled by multiple network elements and cross multiple communication links as it travels between its source and its destination over the network.
Optical fibers are commonly used to implement communication links. To communicate using an optical fiber, light is modulated at one end of the fiber and the modulated light is detected at the other end. Different wavelengths may be used simultaneously, so that multiple signals may be carried on the same fiber. FIG. 1 shows an example optical network 10 in which network elements 12 are connected to opposite ends of a link 14. Optical interfaces 16 on the network elements transmit and receive data over the optical link 14.
As shown in FIG. 1, a network element will use an optical interface to transmit light onto the optical fiber. As transmission speeds have increased over time, the manner in which the optical interfaces are implemented has likewise changed. For example, it is now possible to transmit 40 Gb/s (OC768/STM-256 or OTU-3) on a given wavelength. To enable the optical interface to transmit this much data, the data may be transmitted between the components forming the optical interface using multiple lower speed channels, and then multiplexed into a single data stream prior to transmission onto the optical fiber.
FIG. 2 shows an example optical interface that may be used to transmit data onto an optical fiber. As shown in FIG. 2, an optical interface generally includes a framer 20 configured to frame data for transmission over multiple data channels 22. The data from the framer is passed through a Forward Error Correction (FEC) processor 24, and then is passed to a serializer/deserializer (SERDES) 26 configured to multiplex the data from the multiple data channels 22 onto an optical fiber 14. Additional details associated with an optical interface of this nature are provided in the SERDES-Framer Interface standard SFI-5, the content of which is hereby incorporated by reference. Other SFI standards exist as well and embodiments of the invention may be adapted to use with those other standards as well. The SFI-5 standard specifies the manner in which the data is to be transmitted on the data channels 22 between the components of the optical interface, such as between the framer and FEC processor, between the FEC processor and the SERDES, and/or between the framer and SERDES. The optical interface in this example supports bidirectional flow of data from the network element to the optics, and from the optics to the network element. The SFI-5 standard may be used to enable communications between the components of the optical interface in both directions.
As shown in FIG. 2, the SFI standard describes a way in which the entire serial optical data stream can be broken down into multiple, lesser rate electrical streams in order to be delivered from one component to the next. These multiple deserialized electrical streams will hereafter be referred to as data lanes or channels. One aspect of the SFI-5 standard is that the data lanes need to be aligned with each other to within a particular tolerance level, so that the receiver is able to correctly extract data from the data lanes. Specifically, the standard specifies that the several data lanes must be aligned to within five Unit Intervals (UI or bits). Although the term “Unit Interval or UI” will be used in connection with alignment of the data lanes so that the language used herein comports with the language used in the SFI-5 standard, the invention is not limited to use in connection with an implementation of that standard. Thus, other alignment values or tolerance levels may be used in other contexts.
To enable the components to determine whether the data lanes are properly aligned, a deskew channel 28 is provided for each set of sixteen data lanes. In operation, the deskew channel is used to transmit a portion of the data from each of the data channels, in turn, that has been sampled at a particular defined time. The receiving component uses this replicated data on the deskew channel to look for the same data on each of the data lanes, in turn, at an expected time. It then uses the measured skew between the data lane and the deskew channel to bring the data lane into alignment with the deskew lane; this receiver operation is referred to as deskewing the data lane. If the receiving component is not able to find the same data on the data channel as was supplied on the deskew channel, the receiving component may infer that the delay on the data channel exceeds its capability to deskew and that the data channel is out of alignment. Since the deskew channel contains data for each data lane (one after another) the receiving component is able to check each data channel to make sure each data channel it is aligned properly. The range within which the SERDES is able to deskew the data will be referred to herein as the capture range. The capture range is typically 2N unit intervals in length (+/−N symbols) from the deskew channel; that is to say that if a data lane's pattern is skewed by less than −N to +N symbol periods from the replicated data on the deskew channel, then the data lane can be deskewed.
The receiving component has an out of alignment alarm 29 that is used to provide feedback when one or more of the data channels is out of alignment. Specifically, if the receiving component determines that one of the data channels 22 is out of alignment, it will indicate this to the transmitting component using an out of alignment alarm. The SFI-5 standard requires a single out of alignment alarm to be provided which indicates that one or more of the data lanes can not be appropriately deskewed. However, there are 16 data channels in the SFI standard, and the alarm is used to indicate that at least one of them is out of alignment without indicating the particular lane that is determined to be out of alignment. Thus, determining which of the lanes is out of alignment may not be trivial.
For cost reasons, it may be advantageous to implement one or more of the components of an optical interface using a Field Programmable Gate Array (FPGA) rather than using an Application Specific Integrated Circuit (ASIC). Additionally, using a FPGA may be more versatile than using an ASIC, since many FPGAs are able to be reprogrammed if necessary to update the logic implemented therein. Unfortunately, the available FPGAs, such as FPGAs available from Altera™ and Xilinx™, generally are only able to achieve an inter-lane alignment of approximately 40 unit intervals, which is well in excess of the maximum inter-lane alignment requirements of 5 unit intervals set by the current implementation of the SFI 5 standard.